The present invention relates to a semiconductor integrated circuit device having vertical type power MOSFETs incorporated on a main surface of a semiconductor substrate, and particularly it relates to a technique of constructing a semiconductor integrated circuit device having power MOSFETs of low ON resistance and bipolar transistors mounted mixedly on the same substrate.
Regarding a technique of forming vertical type power MOSFETs on the main surface of a semiconductor substrate, descriptions are found in the Electronic Materials, Kabushiki Kaisha Kogyo Chosakai, September, 1981, pp. 22 to 28, and others. The object of this technique, however, is a discrete power MOSFET.
Besides, proposals have been made by the Motorola Company Incorporated and others on IC wherein vertical type power MOSFETs are formed in parts on a main surface of a semiconductor substrate and bipolar transistors are constructed on another part of the main surface thereof
Said IC wherein the vertical type power MOSFETs and the bipolar transistors are formed on the same substrate has a structure, for instance, as shown in FIG. 9.
As shown in FIG. 9, an n.sup.+ type buried layer 2a for reducing a drain resistance of a vertical type power MOSFET Q.sub.1 an n.sup.+ type buried layer 2b for reducing a collector resistance of an NPN-type bipolar transistor BIP are provided selectively on the surface of a p.sup.- type silicon substrate 1. Moreover, an n.sup.- type epitaxial layer 3 is formed on the whole surface of said p.sup.- type silicon substrate 1. Said n.sup.- type epitaxial layer 3 is separated electrically to form a plurality of insular (or island) regions by p-type isolation layers 5. In one of said insular regions, the vertical type power MOSFET Q.sub.1 comprises a gate electrode 6 made of polysilicon, a source region 8 and a drain region 3a is formed. A p-type diffused region 7 forms a channel region of said vertical type power MOSFET Q.sub.1. Numeral 4 denotes a gate insulating film. Moreover, a drain lead-out region 10a formed by diffusing n-type impurities from the surface of the n.sup.- type epitaxial layer 3 is connected electrically to the n.sup.+ type buried layer 2a which becomes a part of the drain region of the vertical type power MOSFET Q.sub.1. A supply potential V.sub.CC (12 V) is impressed, for instance, on said drain lead-out region 10a. A current path I at the time of operation of the vertical type power MOSFET runs through the drain regions 2a, 3a from the drain lead-out region 10a as shown in the same figure. It runs further through the channel region (p-type diffused region 7), reaches the source region 8 and is outputted outside. Resistance R.sub.1, R.sub.2 are parasitic resistances of the drain regions 3a, 2a themselves.
In the insular region adjacent to the insular region in which the vertical type power MOSFET is formed, the NPN-type bipolar transistor BIP comprising an emitter region 8b, a base region 7b and a collector region 3b is formed. Besides, an n.sup.+ type diffused layer 10b for leading out a collector is connected electrically to the n.sup.+ type buried layer 2b.